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as8202nf ttp-c2nf communication c ontroller d ata sheet rev.1.7, february 2007 ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2 000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 2 copyright 2000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, without the prior permission in writing by the copyright holder. to the best of its knowledge, austriamicrosystems ag asserts that the information contained in this publication is accurate and correct. ttp is a registered trademark of fts computertechnik gmbh. all other trademarks are the property of their respective holders. ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2 000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 3 t a b l e o f c o n t e n t s 1. general description ................................................................................................ 4 2. benefits......................................................................................................................... 5 3. key features ............................................................................................................... 5 4. pin assignment ............................................................................................................ 6 5. pin description ........................................................................................................... 6 5.1. p in d irections .........................................................................................................................7 6. electrical specifications...................................................................................... 7 6.1. a bsolute m aximum r atings (n on o perating ) .................................................................. 7 6.2. r ecommended o perating c onditions ................................................................................7 6.3. dc e lectrical c haracteristics .........................................................................................8 8. application information......................................................................................... 9 8.1. h ost cpu i nterface ..............................................................................................................9 8.2. r eset and o scillator .........................................................................................................13 8.3. ttp b us i nterface ...............................................................................................................15 8.4. ttp a synchronous b us i nterface ..................................................................................15 8.5. ttp s ynchronous b us i nterface ....................................................................................15 8.6. t est i nterface ......................................................................................................................16 8.7. led s ignals ...........................................................................................................................17 9. package....................................................................................................................... 18 10. ordering information and support ............................................................. 20 11. related products ............................................................................................... 20 appendix ............................................................................................................................. 21 f eature c omparison .......................................................................................................................21 l ist of a pplication n otes ..............................................................................................................22 l ist of k nown b ugs .........................................................................................................................22 ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2 000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 4 1 . g e n e r a l d e s c r i p t i o n the as8202nf communication controller is an integrated device supporting serial co mmunication according to the ttp ? specification version 1.1. it performs all communication t asks such as reception and transmission of messages in a ttp cluster without interaction of the host cpu. ttp provides mechanisms that allow the deployment in high-dependability distributed real-time systems. it provides the following services: predictable transmission of messages with minimal jitter fault-tolerant distributed clock synchronization consistent membership service with small delay masking of single faults the cni (communication network interface) forms a temporal firewall. it decouples the controller network from the host subsystem by use of a dual ported ram (cni). this prevents the propagation of control errors. the interface to the host cpu is implemented as a 16-bit wide non-multiplexed asynchronous bus interface. ttp follows a conflict-free media access strategy called time division multiple access (tdma). this means, ttp deploys a time slot technique based on a global time that is permanently synchronized. each node is assigned a time slot in which it is allowed to perform transmit operation. the sequence of time slots is called tdma round, a set of tdma rounds forms a cluster cycle. the operation of the network is repeated after one cluster cycle. the sequence of interactions forming the cluster cycle is defined in a static time schedule, called message descriptor list (medl). the definition of the medl in conjunction with the global time determines the response time for a service request. the membership of all nodes in the network is evaluated by the communications controller. this information is presented to all correct cluster members in a consistent fashion. during operation, the status of all other nodes is propagated within one tdma round. please read more about ttp and request the ttp specification at www.tttech.com . rxd[1:0] rxclk[1:0] rxdv[1:0] rxer[1:0] xin1 xout1 txd[1:0] cts[1:0] txclk[1:0] ram_clk _ testse ftest stest fidis ttest d[15:0] a[11:0] ceb oeb web readyb intb led[2:0] ram_clk_testse use_ram_clk xin0 xout0 plloff resetb quartz or oscillator communi- cation network interface (cni) --------------------- network configuration memory (medl) ttp protocol processor core instruction memory ram & rom test interface ttp bus media drivers bus guardian receiver transmitter reset & time base host processor interface test inter- face figure 1. as8202nf block diagram ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2 000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 5 2 . b e n e f i ts the as8202nf provides support for fault-tolerant, high-speed bus systems in a single device. t he communication controller is qualified for the full temperature range required for automotive applications and is certifiable according to rtca standards. it offers superior reliability and supports data transfer rates of 25 mbit/s with mii and up to 5 mbit/s with mfm/manchester. the as8202nf is the first ttp controller to support both mfm and manchester coding. manchester coding is important for dc-free data transmission, which allows the use of transformers in the data stream. the as8202nf is pin-compatible with its predecessor, the as8202. 3 . k e y f e a t u r e s d edicated controller supporting ttp (time-triggered protocol class c) suited for dependable distributed real-time systems with guaranteed response time application fields: automotive (by-wire braking, steering, vehicle dynamics control, drive train control), aerospace (aircraft electronic systems), industrial systems, railway systems asynchronous data rate up to 5 mbit/s (mfm / manchester) synchronous data rate 5 to 25 mbit/s bus interface (speed, encoding) for each channel selectable independently 40 mhz main clock with support for 10 mhz crystal, 10 mhz oscillator or 40 mhz oscillator 16 mhz bus guardian clock with support for 16 mhz crystal or 16 mhz oscillator single power supply 3.3v, 0.35m cmos process full automotive temperature range (-40c to 125c) 16k x 16 sram for message, status, control area (communication network interface) and for scheduling information (medl) 4k x 16 (plus parity) instruction code ram for protocol execution code data sheet conforms to protocol revision 2.03 16k x 16 instruction code rom containing startup execution code and deprecated protocol code revision 1.00 16 bit non-multiplexed asynchronous host cpu interface 16 bit risc architecture software tools, design support, development boards available ( www.tttech.com ) 80 pin lqfp80 package ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2 000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 6 4 . p i n as s i g n m e n t ceb vss vddbg d15 d14 d13 d12 readyb xin1 vssbg web oeb d11 d10 d9 d8 vdd ttest vsspll xout1 vss vdd a3 a4 vss fidis xin0 nc xout0 txd0 vddpll cts0 rxer0 txclk0 rxclk0 rxd0 rxdv0 vdd txd1 vss cts1 rxer1 txclk1 rxclk1 rxd1 rxdv1 d7 d5 d6 d4 d2 d3 d1 d0 vdd a10 a11 a9 a7 a8 a6 vss a5 resetb vss intb vdd nc led1 led2 led0 u se_ram_clk nc a0 a1 a2 1 20 21 40 41 60 61 80 ftest plloff stest ram_clk_testse as8202nf ttp communications controller (top view) figure 2. lqfp 80 pin package and pin assignment 5 . p i n d e s c r i p t i o n pin n ame dir function 12,29,49,59,74 vdd p positive power supply 13,30,41,50,60,75 vss p negative power supply 70 vddbg p positive power supply for bus guardian (connect to vdd) 73 vssbg p negative power supply for bus guardian (connect to vss) 4 vddpll p positive power supply for main clock pll (connect to vdd) 80 vsspll p negative power supply for main clock pll (connect to vss) 21 ram_clk_testse i pd r am_clk when stest='0' and use_ram_clk='1', else test input, connect to vss if not used 22 stest i pd test input, connect to vss 24 ftest i pd test input, connect to vss 25 fidis i pd test input, connect to vss 61 ttest i pu test input, connect to vdd 34 use_ram_clk i pd ram_clk pin enable, connect to vss if not used 2 xin0 a main clock: analog cmos oscillator input, use as input when providing external clock 3 xout0 a main clock: analog cmos oscillator ouptut, leave open when providing external clock 23 plloff i pd m ain clock pll disable pin, connect to vss when providing 10 mhz crystal for enabling the internal pll 72 xin1 a bus guardian clock: analog cmos oscillator input, use as input when providing external clock 71 xout1 a bus guardian clock: analog cmos oscillator output, leave open when providing external clock 26 resetb i pu main reset input, active low 5 txd0 o pu ttp bus channel 0: transmit data 6 cts0 o pd ttp bus channel 0: transmit enable 11 rxd0 i pu ttp bus channel 0: receive data 7 txclk0 i pd ttp bus channel 0: transmit clock (mii mode) ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2 000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 7 pin name dir function 8 rxer0 i pu ttp bus channel 0: receive error (mii mode) 9 rxclk0 i pd ttp bus channel 0: receive clock (mii mode) 10 rxdv0 i pu ttp bus channel 0: receive data valid (mii mode) 14 txd1 o pu ttp bus channel 1: transmit data 15 cts1 o pd ttp bus channel 1: transmit enable 20 rxd1 i pu ttp bus channel 1: receive data 16 txclk1 i pd ttp bus channel 1: transmit clock (mii mode) 17 rxer1 i pu ttp bus channel 1: receive error (mii mode) 18 rxclk1 i pd ttp bus channel 1: receive clock (mii mode) 19 rxdv1 i pu ttp bus channel 1: receive data valid (mii mode) 35-39, 42-48 a[11:0] i host interface (cni) address bus 1 51-58, 62-69 d[15:0] i/o host interface (cni) data bus, tristate 76 ceb i pu host interface (cni) chip enable, active low 77 oeb i pu host interface (cni) output enable, active low 78 web i pu host interface (cni) write enable, active low 79 readyb o pu host interface (cni) transfer finish signal, active low, open drain 2 28 intb o pu host interface (cni) time signal (interrupt), active low, open drain 31-33 led[2:0] o pd configurable generic output port 1, 27, 40 nc not connected, leave open note 1: the device is addressed at 16-bit data word boundaries. if the device is connected to a cpu with a byte-granular address bus, remember that a[11:0] of the as8202nf device has to be connected to a[12:1] of the cpu (considering a little endian cpu address bus). note 2: at de-assertion readyb is driven to the inactive value (high) for a configurable time. 5.1. pin directions dir f unction i ttl input i pu ttl input with internal weak pull-up i pd ttl input with internal weak pull-down i/o ttl input/output with tristate o pu ttl output with internal weak pull-up at tristate o pd ttl output with internal weak pull-down at tristate a analog cmos pin p power pin 6 . e l e c t r i c a l s p e c i f i c a t i o n s 6.1. absolute maximum ratings (non operating) parameter sy mbol conditions min typ max unit dc supply voltage vdd -0.3 5.0 v input voltage vin any pin -0.3 vdd+0.3 v input current iin any pin, ta=25c -100 100 ma storage temperature tstrg -55 150 c soldering temperature tsold t=10 sec, reflow and wave 235 c humidity h 5 85 % electrostatic discharge esd hbm: 1kv mil.std.883, method 3015.7 1000 v note: stresses higher than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device under these or any other conditions higher than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability (e.g. hot carrier degradation). 6.2. recommended operating conditions parameter sy mbol conditions min typ max unit dc supply voltage 1 v dd vss=0v 3.0 3.3 3.6 v ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2 000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 8 ambient temperature 1 t a -40 125 c static supply current idds all inputs tied to vdd/vss, clocks stopped, exclusive of i/o drive requirements, vdd=3.6v 5 900 a operating supply current 2 i dd vdd=3.3v, pll active, exclusive of i/o drive requirements 100 4 ma clk0_ext_pll pll active 3 100 ns clock period of main clock (external) 2 c lk0_ext pll inactive 25 ns clock period of bus guardian clock 2 c lk1 62.5 ns note 1: the input and output parameter values in this table are directly related to ambient temperature and dc supply voltage. a temperature range other than ta min to ta max or a supply voltage range other than vdd min to vdd max will affect these values and must be evaluated on its own. n ote 2: typical values: clk0=40 mhz, clk1=16 mhz note 3: using the internal pll multiplies the main clock frequency by 4. note 4: to be defined 6.3. dc electrical characteristics ttl input pins and ttl bidirectional pins in input/tristate mode parameter sy mbol conditions min 1 t yp max 1 u nit input low voltage vil 0.8 v input high voltage vih 2.0 v input leakage current iin pins without pad resistors, vdd=3.6v 1 a vin=0.4v 4.9 3 pins with pull- down resistors vdd=3.0v vin=0.8v 8.8 3 input low current iil pins with pull-up resistors vdd=3.6v vin=0v -15 -75 a pins with pull- down resistors vdd=3.6v vin=3.6v 15 75 vin=2.0v -10.7 3 input high current iih pins with pull-up resistors vdd=3.0v vin=2.5v -6 3 a input capacitance cin 4.5 2 pf cmos inputs (xin), drive from external clock generator drive at xin (xout = open) parameter sy mbol conditions min 1 t yp max 1 u nit input capacitance c_xin input slope 2ns, vil=0v, vih=3.3v, vdd=3.3v 1.9 2.5 pf input current iin_xin 1 2 a input low voltage vil_xin 0 0.3*vdd v input high voltage vih_xin 0.7*vdd vdd v outputs and ttl bidirectional pins in output mode parameter sy mbol conditions min 1 t yp max 1 u nit output low current iol vdd=3.0v, vo = 0.4v -4 ma output high current ioh vdd=3.0v, vo = 2.5v 4 ma output tristate current ioz vdd=3.6v 10 2 a txd[1,0], cts[1,0], led[2:0], intb 8.1 3 transition time C rise tr t(vout=0.1*vdd) t o t(vout=0.9*vdd) t = 125 c, s low process, vdd=3.0v, cload=35pf d[15:0], readyb 8.9 3 n s ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2 000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 9 txd[1,0], cts[1,0], led[2:0], intb 6 3 transition time C fall tf t(vout=0.9*vdd) t o t(vout=0.1*vdd) t = 125 c, s low process, vdd=3.0v, cload=35pf d[15:0], readyb 7 3 n s note 1: if min/max values are both negative, they are ordered according to their absolute value. note 2: typical value, not tested during production. note 3: implicitly tested. 8 . ap p l i c a t i o n i n f o r m a t i o n 8.1. host cpu interface the host cpu interface, also referred to as cni (communication network interface), connects t he application circuitry to the as8202nf ttp controller. all related signal pins provide an asynchronous read/write access to a dual ported ram located in the as8202nf. there are no setup/hold constraints referring to the microtick (main clock clk0). all accesses have to be executed on a granularity of 16 bit (2 byte), the device does not support byte-wide accesses. pin a0 (lsb) of the device differentiates even and odd 16 bit word addresses and is typically connected to a1 of a little-endian host cpu. a0 of the host cpu is not connected to the device, and the application/driver on the host cpu should force all accesses to be 16 bit. for efficiency reasons, the host cpu appliation/driver may access some memory locations of the as8202nf using wider accesses (e.g. 32 bit), and the bus interface of the host cpu will automatically split the access into two consecutive 16-bit wide accesses to the ttp controller. note that particularly in such a setup all timing parameters of the host cpu interface must be met, especially the inactivity timeouts described as symbols 16C19. the host interface features an interrupt or time signal intb to notify the application circuitry of programmed and protocol-specific, synchronous and asynchronous events. the host cpu interface allows access to the internal instruction code memory. this is required for proper loading of the protocol execution code into the internal instruction code ram, for extensive testing of the instruction code ram and for verifying the instruction code rom contents. intb is an open-drain output, i.e. the output is only driven to '0' and is weak-pull-up at any other time, so external pull-up resistors or transistors may be necessary depending on the application. readyb is also an open-drain output, but with a possibility to be driven to 1 for a defined time (selectable by register) before weak-pull-up at any other time. the led port is software-configurable to automatically show some protocol-related states and events, see below for the led port configuration. host interface ports pin name mode width comment a[11:0] in 12 cni address bus, 12 bit (a0 is lsb) d[15:0] inout (tri) 16 cni data bus, 16 bit (d0 is lsb) ceb in 1 cni chip enable, active low web in 1 cni write enable, active low oeb in 1 cni output enable, active low readyb out (open drain) 1 cni ready, active low ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2 000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 10 pin name mode width comment intb out (open drain) 1 cni interrupt, time signal, active low ram_clk_testse in 1 host clock use_ram_clk in 1 host clock pin enable asynchronous readyb permits the shortest possible bus cycle but eventually requires signal synchronization in the application. connect use_ram_clk to vss to enable this mode of operation. synchronous readyb uses an external clock (usually the host processors bus clock) for synchronization of the signal eliminating external synchronization logic. connect use_ram_clk to vdd and ram_clk_testse to the host processor's bus clock to enable this mode of operation. note: due to possible metastability occurrence, it is not recommended to be used in safety critical systems. ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2 000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 11 asynchronous dpram interface parameter sym bol conditions min typ max unit controller cycle time tc 25 ns 1a a[11:0] input valid to ceb, web (setup time) 2a d[15:0] 5 ns 1b a[11:0] 3 ceb, web to input invalid (hold time) 2b d[15:0] 4 ns input rising to ceb, web falling 3 ceb, web, oeb 5 1,2 ns ceb, web rising to input falling 4 ceb, web, oeb 5 1,2 ns write access time (ceb, web to readyb) 5 min = 1 tc, max = 4 tc 25 100 ns ceb, web de-asserted to readyb de- asserted 6 9.4 ns input valid to ceb, oeb (setup time) 7a a[11:0] 5 ns ceb, oeb to input invalid (hold time) 7b a[11:0] 2 ns input rising to ceb, oeb falling 8 ceb, web, oeb 5 1 ns ceb, oeb rising to input falling 9 ceb, web, oeb 5 1 ns read access time (ceb, oeb to readyb) 10 min = 1.5 tc, max = 8 tc 37.5 200 ns ceb, oeb asserted to signal asserted 11a d[15:0] 4.0 8.4 ns 11b d[15:0] 3.8 8 ceb, oeb de-asserted to signal de- asserted 11c readyb 8.8 ns readyb, d skew 12 2 ns ram_clk_testse rising to readyb falling 13 use_ram_clk='1' 3.7 13.5 ns ram_clk_testse rising to readyb rising 14 use_ram_clk='1' 3 9.7 ns ready delay='00' 3.6 12.9 ready delay='01' 4.5 15.4 ready delay='10' 5.4 18.8 ram_clk_testse rising to readyb deactivated 1->z 15 use_ram_clk ='1' ready delay='11' 6.4 22.2 ns read to read access inactivity time (ceb, oeb low to ceb, oeb low) 16 min = 1.5 tc 37.5 1 ns read to write access inactivity time (ceb, oeb low to ceb, web low) 17 5 1 ns write to write access inactivity time (ceb, web low to ceb, web low) 18 5 1,2 ns write to read access inactivity time (ceb, web low to ceb, oeb low) 19 5 1,2 ns note 1: prior to starting a read or write access, ceb, web and oeb have to be stable for at least 5 ns (see symbol 3, 4, 8, 9). in addition the designer has to consider the minimum inactivity time according to symbols 16, 17, 18, 19. see figure 3 for more information on the inactivity times. note 2: to allow proper internal initialization, after finishing any write access (ceb or web is high) to the internal controller_on register, ceb oeb and web have to be stable high within 200 ns ( min = 8 tc). note: all values not tested during production, guaranteed by design. ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2 000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 12 ceb web oeb 16 read read 18 write 17 write 19 read figure 3 . read/write access inactivity time w rite access timing (ceb controlled) write access timing (web controlled) ceb web a valid valid d oeb readyb 1a 1b 2a 2b 3 6 5 4 ceb web a valid valid d oeb readyb 1a 1b 2a 2b 6 5 3 4 read access timing (ceb controlled) read access timing (oeb controlled) ceb web a valid d oeb readyb 7a 7b 8 11c 10 9 12 invalid valid 11a 11b ceb web a valid d oeb readyb 7a 7b 8 11c 10 9 12 invalid valid 11a 11b figure 4 . host read/write access timing ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 13 synchronous readyb generation figure 5 . synchronous readyb timing s ynchronous readyb is aligned to host clock (with pulse duration of one host clock cycle) to fulfill the required host timing constraints for input setup and input hold time to/after host clock rising edge. note: connect use_ram_clk to vdd and ram_clk_testse to the host processor's bus clock to enable this mode of operation. due to possible metastability occurrence, it is not recommended to be used in safety critical systems. 8.2. reset and oscillator pin name mode comment xin0 analog main oscillator input (external clock input) xout0 analog main oscillator output xin1 analog bus guardian oscillator input (external clock input) xout1 analog bus guardian oscillator output plloff in pll disable resetb in external reset external reset signal to issue a reset of the chip the resetb port has to be driven low for at least 1 us. pulses under 50 ns duration are discarded. at power-up the reset must overlap the build-up time of the power supply. integrated power-on reset the device has an internal power-on reset generator. when supply voltage ramps up, the internal reset signal is kept active (low) for 33 s typical. parameter symbol min typ max unit supply voltage slope dv/dt 551 - - v/ms power on reset active time after vdd > 1,0v tpores 25 33 49 s note 1: in case of non-compliance keep the external reset (resetb) active for min. 5 ms after supply voltage is valid and oscillator inputs active. o scillator circuitry the internal oscillators for main and bus guardian clock require external quartzes or external oscillators. the main clock features a pll multiplying a 10 mhz xin0/xout0 oscillation to an internal frequency of 40 mhz when enabled. asynchronous readyb ram_clk_testse synchronous readyb 13 14 15 ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 14 xin0 xout0 plloff vss 10 mhz rd rf cext cext xin0 xout0 plloff vss 10 mhz square wave xin0 xout0 plloff vdd 40 mhz square wave enabled pll, external quartz enabled pll, external oscillator disabled pll, external oscillator figure 6. main clock setup r f will normally not be soldered, it is only provided to get maximum flexibility. cext, typ = 15/18 pf. rd has to be calculated, if the measured drive level will be too high; if drive level is ok, rd = 0. if using an external oscillator at 10 mhz with enabled internal pll, the oscillator must have a period of 100 ns with low jitter. note that a crystal-based clock is recommended over a derived clock (i.e., pll-based) to allow best internal pll performance. parameter c onditions min typ max unit r_osc10 oscillation margin @ 10 mhz, cload = 18 pf 0.95 1 1.62 1 kohm r_osc16 oscillation margin @ 16 mhz, cload = 18 pf 0.37 1 0.64 1 kohm r_osc20 oscillation margin @ 20 mhz, cload = 18 pf 0.24 1 0.41 1 kohm note 1: not tested during production. cload is the value of the external load capacitors towards ground. the total load capacitance seen by the quartz will be cload_tot = (cload + cpar)/2. cpar is the equivalent parasitic capacitance of the oscillator cell inputs and the pcb and is derived from measurements to be about 3.5 4.0 pf. t he bus guardian clock has no internal pll and must be connected to either a 16 mhz quartz or an external 16 mhz oscillator: xin1 xout1 16 mhz rd rf cext cext xin1 xout1 16 mhz square wave external quartz external oscillator figure 7. bus guardian clock setup both the xin0/xout0 (main clock) and the xin1/xout1 (bus guardian clock) cells support d riving a quartz crystal oscillation as well as clock input by an external oscillator. build-up characteristics parameter symbol pin min typ max note oscillator startup time (main clock) tosc_startup0 xin0/xout0 20 ms quartz frequency: 10 mhz oscillator startup time (bus guardian clock) tosc_startup1 xin1/xout1 20 ms quartz frequency: 16 mhz ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 15 parameter symbol pin min typ max note pll startup time (main clock) tpll_startup0 xin0/xout0 20 ms quartz frequency: 10 mhz 8.3. ttp bus interface the as8202nf contains two ttp bus units, one for each ttp channel, building the ttp bus i nterface. each ttp bus channel contains a transmitter and a receiver and can be configured to be either in the asynchronous or synchronous mode of operation. note that the two channels (channel 0 and channel 1) can be configured independently for either of these modes. the drivers of the txd and cts pins are actively driven only during a transmission window, all the other time the drivers are switched off and the weak pull resistors are active. external pull resistors must be used to define the signal levels during idle phases. note that the transmission window may be different for each channel. pin name tx inactive txd[0] weak pull-up cts[0] weak pull-down txd[1] weak pull-up cts[1] weak pull-down 8.4. ttp asynchronous bus interface when in asynchronous mode of operation the channel's bus unit uses a self-clocking t ransmission encoding which can be either mfm or manchester at a maximum data rate of 5 mbit/s on a shared media (physical bus). the pins can either be connected to drivers using recessive/dominant states on the wire as well as drivers using active push/pull functionality. the rxd signal uses '1' as the inactivity level. in the so-called rs485 compatible mode longer periods of '0' are treated as inactivity, too. if the rs485 compatible mode is not used, the application must care to drive rxd to '1' during inactivity on the bus. pin name mode connect to phy comment txd[0] out txd transmit data channel 0 cts[0] out cts transmit enable channel 0 txclk[0] in no function (do not connect) rxer[0] in no function (do not connect) rxclk[0] in no function (do not connect) rxdv[0] in no function (do not connect) rxd[0] in rxd receive data channel 0 txd[1] out txd transmit data channel 1 cts[1] out cts transmit enable channel 1 txclk[1] in no function (do not connect) rxer[1] in no function (do not connect) rxclk[1] in no function (do not connect) rxdv[1] in no function (do not connect) rxd[1] in rxd receive data channel 1 8.5. ttp synchronous bus interface when in synchronous mode of operation, the bus unit uses a synchronous transfer method to t ransfer data at a rate between 5 and 25 mbit/s. the interface is designed to run at 25 mbit/s ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 16 and to be gluelessly compatible with the commercial 100 mbit/s ethernet mii (media independent interface) according to ieee standard 802.3 (ethernet csma/cd). connecting the synchronous ttp bus unit to a 100 mbit/s ethernet phy is done by connecting txd, cts, txclk, rxer, rxclk, rxdv and rxd of any channel to txd0, txen, txclk, rxer, rxclk, rxdv and rxd0 of the phy's mii. the pins txd1, txd2 and txd3 of the phy's mii should be linked to vss. the signals rxd1, rxd2, rxd3, col and crs as well as the mmii (management interface) should be left open or can be used for diagnostic purposes by the application. note that the frames sent by the as8202nf are not ethernet compatible and that an ethernet hub (not a switch) can be used as a 'star coupler' for proper operation. also note that the ethernet phy must be configured for full duplex operation (even though the hub does not support full duplex), because ttp has its own collision management that should not interfere with the phy's half-duplex collision management. in general, the phy must not be configured for automatic configuration ('auto negotiation') but be hard-configured for 100 mbit/s, full duplex operation. note that to run the interface at a rate other than 25 mbit/s other transceiver phy components have to be used. pin name mode connect to phy comment txd[0] out txd0 transmit data channel 0 cts[0] out txen transmit enable channel 0 txclk[0] in txclk transmit clock channel 0 rxer[0] in rxer receive error channel 0 rxclk[0] in rxclk receive clock channel 0 rxdv[0] in rxdv receive data valid channel 0 rxd[0] in rxd0 receive data channel 0 txd[1] out txd0 transmit data channel 1 cts[1] out txen transmit enable channel 1 txclk[1] in txclk transmit clock channel 1 rxer[1] in rxer receive error channel 1 rxclk[1] in rxclk receive clock channel 1 rxdv[1] in rxdv receive data valid channel 1 rxd[1] in rxd0 receive data channel 1 8.6. test interface the test interface supports the manufacturing test and characterization of the chip. in the a pplication environment test pins have to be connected as following: stest, ftest, fidis: connect to vss ttest: connect to vdd warning: any other connection of these pins may cause permanent damage to the device and to additional devices of the application. ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 17 8.7. led signals the led port consists of three pins. via the medl each of these pins can be independently co nfigured for any of the three modes of operation. at power-up and after reset the led port is inactive and only weak pull-down resistors are connected. after the controller is switched on by the host and when it is processing its initialization, the led port is initialized to the selected mode of operation. pin name protocol mode timing mode bus guardian mode led2 rpv 1 or protocol activity 7 time overflow 2 action time 4 led1 sync valid 8 time tick 2 bde1 5 led0 protocol activity 6 or rpv 7 microtick 3 bde0 5 note 1: rpv is remote pin voting. rpv is a network-wide agreed signal used typically for agreed power-up or power-down of the application's external drivers. note 2: time overflow is active for one clock cycle at the event of an overflow of the internal 16-bit time counter. time tick is active for one clock cycle when the internal time is counted up. time overflow and time tick can be used to externally clone the internal time control unit (tcu). with this information the application can precisely sample and trigger events, for example. note 3: microtick is the internal main clock signal. note 4: action time signals the start of a bus access cycle. note 5: bde0 and bde1 show the bus guardian's activity, '1' signals an activated transmitter gate on the respective channel. note 6: protocol activity is typically connected to an optical led. the flashing frequency and rhythm give a simple view to the internal ttp protocol state. note 7: led2's rpv mode and led0's protocol activity mode can be swapped with a medl parameter. note 8: the controller sets this output when cluster synchronization is achieved (after integration from the listen state, after acknowledge in the coldstart state). e ach led pin can be configured to be either a push/pull driver (drives both low and high) or to be only an open-drain output (drives only low). ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 18 9 . p a c k a g e type: lqfp80 j a la n s . p a rm an kav. 201 ba ta m ind o ind us tria l p a rk, muka kuning ba ta m is la nd 29433, indonesia ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 19 j a la n s . p a rm an kav. 201 ba ta m ind o ind us tria l p a rk, muka kuning ba ta m is la nd 29433, indonesia ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 20 1 0 . o r d e r i n g i n f o r m a t i o n a n d s u p p o r t part number: as8202nf p art name: ttp-c2nf communication controller package: lqfp80 please contact one of the following austriamicrosystems sales offices for further assistance: headquarters a ustriamicrosystems ag a-8141 schloss premst?tten austria tel.: +43 3136 500-0 fax: +43 3136 525-01 e-mail: info@austriamicrosystems.com web: www.austriamicrosystems.com sales offices north america austriamicrosystems usa, inc. suite 400, 8601 six forks road raleigh, nc 27615 usa tel.: +1 919 676 5292 fax: +1 509 696 2713 sales offices europe austriamicrosystems germany gmbh tegernseer landstrasse 85 d-81539 mnchen germany tel.: +49 89 693643-0 fax: +49 89 693643-66 austriamicrosystems usa, inc. suite 116, 4030 moorpark ave, san jose, ca 95117 usa tel.: +1 408 345 1790 fax: +1 509 696 2713 austriamicrosystems italy s.r.l. piazzale marengo 8, i 20121 milano italy tel.: +39 02 4565 910 fax: +39 02 4892 0265 sales offices asia austriamicrosystems ag suite 811, tsimshatsui centre, east wing, 66 mody road, tsim sha tsui east, kowloon hong kong tel.: +852 2268 6899 fax: +852 2268 6799 austriamicrosystems uk 88, barkham ride, finchampstead, wokingham berks. rg40 4et, uk. tel.: +44 118 973-1797 fax: +44 118 973-5117 austriamicrosystems ag singapore representative office 83 clemenceau avenue #02-01 ue square, singapore 239920 tel.: +65 68 30 83 05 fax: +65 62 34 31 20 austriamicrosystems switzerland ag rietstrasse 4 ch-8640 rapperswil switzerland tel.: +41 55 220 9000 f ax: +41 55 220 9001 austriamicrosystems ag aios gotanda annex 5th fl., 1-7-11, higashi-gotanda, shinagawa-ku tokyo 141-0022 japan tel.: +81 3 5792 4975 fax: +81 3 5792 4976 austriamicrosystems france s.a.r.l. 124, avenue de paris f-94300 vincennes france tel.: +33 1 43 74 00 90 fax: +33 1 43 74 20 98 austriamicrosystems ag #805, dong kyung bldg., 824-19, yeok sam dong, kang nam gu, seoul korea 135-080 tel.: +82 2 557 8776 fax: +82 2 569 9823 1 1 . r e l a t e d p r o d u c ts software tools, hardware development boards, evaluation systems and extensive support on t tp system integration as well as consulting are provided by: ttchip entwicklungsgesellschaft mbh sc hoenbrunner strasse 7 a-1040 vienna, austria tel.: +43 1 5853434-0 fax: +43 1 5853434-90 e-mail: office@ttchip.com web: www.ttchip.com tttech computertechnik ag schoenbrunner strasse 7 a-1040 vienna, austria tel.: +43 1 5853434-0 fax: +43 1 5853434-90 e-mail: support@tttech.com web: www.tttech.com ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 21 ap p e n d i x feature comparison feature c2 as8202 c2nf as8202nf conformance with ttp specification version 1.0. yes yes ttp controller risc cpu (pcu) risc cpu (pcu) firmware on chip yes (flash) no 1 data load phase at power-on no (medl in flash) yes (medl in ram) interface to ttp physical layer - asynch. - synch.(mii) - asynch. - synch.(mii) ttp bus data coding (asynchronous interface) mfm mfm manchester ifg (inter frame gap) 45s 23s interface to host cpu 16 bit 16 bit supported host cpu bus type intel intel host cpu access speed (without read ahead) <250ns <150ns (intel) read ahead / posted write no yes (access time <100ns) cni-ram configuration fixed configurable (4kb to 28kb in 4kb steps) medl check method one crc (firmware) ?block crc (firmware) instruction ram (i-ram) check method once (firmware) parity bit (+firmware) support for x-frames yes yes baudrate on ttp bus asynchronous mode synchronous mode up to 5mbd 25mbd up to 5mbd up to 25mbd process 0,35 cmos+flash 0,35 cmos sram 12kbyte 40kbyte rom 8kbyte 32kbyte 1 flash 32kbyte - power supply 3,3v 3,3v temperature range (c) 0 to +70 -40 to +125 package lqfp80 lqfp80 note 1: the chip is designed to allow inclusion of a stable protocol code (or customized protocol code) into the rom by changing the rom mask in the production process. this would eliminate the need of loading the protocol firmware code into the instruction code ram. ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 22 list of application notes the following is a list of the public application notes of the as8202nf: an118 appnote phys layer for ttp/c an120 receiver bug 001 in as8202nf an123 host read accesses speedup in as8202nf an137 as8202nf (ttp/c-c2nf controller) connected to mpc555 microcontroller an145 ttp/c protocol binary release 2.04 for the as8202nf controller an147 as8202nf / c2nf - crc calculation an150 as8202nf tasm software v2.04 mfm rs485 bug an151 as8202nf (ttp/c-c2nf controller) connected to mii transceiver an153 ttp/c controller as8202nf user constraints document an154 as8202nf host view of membership during controller acknowledgement phase an155 as8202nf big bang configuration constraints an156 application constraints using as8202nf timer interrupt an157 constraints using mfm encoding on as8202nf an158 constraints read access of last word in a memory page of the as8202nf the following is a list of the internal application notes of the as8202nf: an115 an116 an121 an124 an146 an148 an149 the following application notes are obsolete for this data sheet: an117 an119 an122 an128 an129 an130 as8202nf manchester decoding bug an131 an132 as8202/as8202nf mfm/mii async reception bug an133 ttp/c protocol binary release 1.02 for the as8202nf controller an134 fix for ignoring ifg traffic during synchronized operation an135 an136 fix for tolerating transformer noise in manchester mode in as8202nf an139 ttp/c protocol binary release 2.02 for the as8202nf controller an140 ttp/c protocol binary release 2.03 for the as8202nf controller an152 data bus instability by read access to the last word in page in as8202nf list of known bugs the following is a list of the known bugs of the as8202nf. 1. as8202nf rx001 receiver bug ttp requires a maximum level of error detection on the physical layer as well as on the semantic layer for a received message. among others the as8202nf has a built-in ability to detect frames that are shorter or longer than expected. this feature does not correctly work for all situations with mfm and manchester encoding. frames that are too short or too long can appear to have the correct size. in this case the crc check invalidates the frame. this bug is reported as bug report an120. ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 23 document revision history r r e e v v i i s s i i o o n n d d a a t t e e m m o o d d i i f f i i c c a a t t i i o o n n a a u u t t h h o o r r 0.1 dec. 17, 2002 initial release matthias w?chter, rastislav hindak 0.2 dec. 18, 2002 a) updated austriamicrosystems logo (front page and header on each page). b) the expected maximum current is now 95 ma instead of 65 ma. the actual tested limits will be given by austriamicrosystems after the first test runs. matthias w?chter 0.3 jan. 9, 2003 a) hbm: r=1.5kohm, c=100pf changed to hbm: 1kv mil.std.883, method 3015.7 b) operating supply current changed to: imin=- , imax=~90ma (tbd) c) soldering temperature changed from 260c to 235c d) updated austriamicrosystems logo (front page and header on each page). e) updated input current values rastislav hindak 0.4 jan. 20, 2003 feature comparison as8202 <-> as8202nf added rastislav hindak 0.4.5 feb. 3, 2003 ceb, oeb to readyb (read access time) C min. = 1 tc changed to 1.5 tc (37.5 ns) asynchronous and synchronous definition of readyb signal changed. rastislav hindak 0.5 feb. 5, 2003 renamed txpadsoff pin with ttest, removed all txpadsoff feature description. synchronous readyb generation added. matthias w?chter rastislav hindak 0.6 feb. 10, 2003 added timing for synchronous readyb figure 3. & 4. updated added max. current for weak-pull input/bidir pads redraw tables, removed typos updated host access inactivity time matthias w?chter rastislav hindak 0.7 mar. 13, 2003 input currents at xin and xout updated rastislav hindak mar. 14, 2003 note 2 on page 7 changed from values not tested, guaranteed by design to typical value, not tested during production. supply voltage slope updated. rastislav hindak 0.8 apr. 3, 2003 appendix C bug list added updated protocol code handling removed oscillator driving at xout rastislav hindak matthias w?chter 0.9 apr. 8, 2003 dc electrical characteristics: ttl input pins and ttl bidirectional pins in input/tristate mode & outputs and ttl bidirectional pins in output mode updated, transition times added, note 3 added. integrated power-on reset C supply voltage slope: note 1 added. host read access inactivity drawing added. rastislav hindak apr. 16, 2003 dc electrical characteristics: outputs and ttl bidirectional pins in output mode: cload changed from 40 pf to 35 pf. oscillator circuitry: oscillation margins added. rastislav hindak apr. 24, 2003 dc electrical characteristics: outputs and ttl bidirectional pins in output mode: parameter output low/high voltage removed. asynchronous dpram interface: common note added. rastislav hindak 1.0 may 23, 2003 added note for clock requirement when using external oscillator and internal pll matthias w?chter ams ag technical content still valid
ttp-c2nf communication controller C data sheet as8202nf rev. 1.7, copyright 2000-2007, austriamicrosystems ag and ttchip entwicklungsgesellschaft mbh. all rights reserved. 24 r r e e v v i i s s i i o o n n d d a a t t e e m m o o d d i i f f i i c c a a t t i i o o n n a a u u t t h h o o r r aug. 6, 2003 updated for protocol v1.02 functionality, updated led functionality according to protocol, added references to all existing public application notes and bug reports matthias w?chter aug. 21, 2003 substitute ttp for ttp/c, add contact page, minor changes in wording and formatting bernhard wenzl aug. 25, 2003 minor changes in wording and formatting matthias w?chter oct. 01, 2003 figure 4.: read access timing (ceb & oeb controlled) updated. timing of asynchronous dpram interface updated (symbol: 1b, 2b, 6, 11 (changed to 11a, 11b, 11c) and 15. rastislav hindak 1.1 oct. 23, 2003 added input capacitance cin for input pins updated values for 11a, 11b updated data sheet, app notes, for protocol version 2.02 matthias w?chter 1.2 nov. 05, 2003 updated data sheet, app notes for protocol version 2.03 matthias w?chter 1.3 may 07, 2004 updated app notes for protocol version 2.04 matthias w?chter 1.4 jul. 15, 2005 updated access inactivity times matthias w?chter 1.5 aug. 16, 2005 updated access inactivity times, read access time matthias w?chter may 16, 2006 pin assignment rotated, note to the synchronous readyb added, application notes an153-158 added rastislav hindak jun. 19, 2006 list of application notes reworked rastislav hindak 1.6 jul. 07, 2006 list of application notes corrected rastislav hindak 1.7 feb. 14, 2007 added clearifications about a[11:0] meaning word addresses matthias w?chter ams ag technical content still valid

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